For near field communication or NFC enabled devices, data transfers may take place between such NFC devices and passive tags. The NFC device may be a reader/writer that communicates with the passive tags. The passive tag receives power from the NFC device to begin the communication. A relatively strong carrier signal may be used to power the passive tag. At the same time power is provided to the passive tag, the NFC device listens for a load modulated signal from the passive tag. In such instances, the so-called load modulation index which measures the amplitude difference between the modulated and unmodulated portions of the carrier signal used to power the passive tag could be less than 0.25%.
The described mode of operation may place significant design requirements for the load modulated signals with such a small load modulation index. In particular, such design requirements may necessitate the use of relatively higher cost analog to digital converters (ADC), such as a 12 bit ADC, and low noise front-end analog circuits.
An NFC device can include a poller. Such a poller can implement a load demodulator followed by a frame detector (which can include an edge detector) for detection of data frames. With the demodulated baseband signals from the load demodulator, the detection of a data frame during an NFC transaction, may involve the following. A frame arrival detection stage is performed by an “edge detector” that reports arrival of data frame arrival when an input sample is larger than a preset threshold. A frame bit detection stage is performed after arrival of a frame is detected. Frame bit detection performance is mainly determined by the false alarm and missing probabilities of the frame arrival of the edge detector and timing recovery accuracy.
Typically, bit boundary detection in bit pollers relies on edge detection and timing recovery. Since an edge detector is sample-based, the edge detector may have to work in low noise environments in order to perform. It is desirable for the edge detector to achieve a low frame miss rate and low false alarm probability. For example, timing recovery is capable of correcting up to +/−16 sample errors, which may be a subcarrier cycle from the frame start as determined by the edge detector. If an error is larger than 16 samples, the timing recovery cannot correct the error, and the frame will be missed.